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programmable frequency scan waveform generator data sheet ad5932 rev. a information furnished by analog devices i s believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice . no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 C 2012 analog devices, inc. all rights reserved. features programmable frequency profile no external components necessary output frequency up to 25 mhz burst - and - listen capability preprogrammable frequency profile minimizes number of dsp/microcontroller writes sinusoidal/triangular/square wave outputs automatic or single pin control of frequency stepping power - down mode : 20 a power supply: 2.3 v to 5.5 v automotive temperature range: ?40c to +125c 16- lead, pb - free tssop applications frequency scanning/radar network/impedance measurements incremental frequency stimulus sensory applications proximity and motion g eneral description the ad5932 1 is a waveform generator offering a progr ammable frequency scan. utilizing embedded digital processing that allows enhanced frequency control, the device generates synthesized analog or digital frequency - stepped waveforms. because frequency profiles are preprogrammed, continuous write cycles are eliminated, thereby freeing up valuable dsp/microcontroller resources. waveforms start from a known phase and are incremented phase - continuously, which allows phase shifts to be easily determined. consuming only 6.7 ma, the ad5932 provides a convenient low power solution to waveform generation. the ad5932 outputs each frequency in the range of interest for a defined length of time and then steps to the next frequency in the scan range. the length of time the device outputs a particular frequency is preprogr ammed, and the device increments the frequency automatically; or, alternatively, the frequency is incremented externally via the ctrl pin. at the end of the range, the ad5932 continues to output the last frequency unt il the device is reset. the ad59 32 also offers a digital output via the msbout pin. (continued on page 3) functional block dia gram ad5932 dvdd cap/2.5v dgnd interrupt st andb y agnd a vdd vcc 2.5v sync mclk ctr l fsync syncout msbout vout com p sclk sdat a dat a and contro l frequenc y controller increment controller contro l register on-board reference full-scale contro l 24-bit pipelined dds core 10-bit dac seria l inter f ace regul a t or dat a incr buffer buffer / 24 05416-001 figure 1. 1 protecte d by u.s. patent number 6747583 .
ad5932 data sheet rev. a | page 2 of 28 table of contents fea tures .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block di agram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 4 specifications test circuit ........................................................... 5 timing specifications .................................................................. 6 master clock and timing diagrams ......................................... 6 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 14 theory of operation ...................................................................... 15 frequency profile ........................................................................ 15 serial interface ............................................................................ 15 powering up the ad5932 .......................................................... 15 programming the ad5932 ........................................................ 16 setting up the frequency scan ................................................. 17 activating and controllin g the scan ....................................... 18 outputs from the ad5932 ........................................................ 19 applications ..................................................................................... 20 groundi ng and layout .............................................................. 20 ad5932 to adsp - 21xx interface ............................................. 20 ad5932 to 68hc11/68l11 interface ....................................... 21 ad5932 to 80c51/80l51 interface .......................................... 21 ad5932 to dsp56002 interface ............................................... 21 evaluation board ............................................................................ 22 schematics ................................................................................... 23 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 2/12 rev. 0 to rev. a change s to figure 21, figure 22, figure 23, figure 24, and figure 25 .......................................................................................... 12 changes to figure 26, figure 27, figure 28, and figure 29 ....... 13 4 /06 revision 0: initial version
data sheet ad5932 rev. a | page 3 of 28 general description (continued from page 1) to program the ad5932, the user enters the start frequency, the increment step size, the number of increments to be made, and the time interval that the part outputs each frequency. the fre - quency scan profile is initiated, started, and executed by tog gling the ctrl pin. the ad5932 is written to via a 3 - wire serial interface that operates at clock rates up to 40 mhz. the device operates with a power supply from 2.3 v to 5.5 v. note that the avdd and dvdd are independent of each other and can be operate d from different voltages. the ad5932 also has a standby function that allows sections of th e device that are not in use to be powered down. the ad5932 is available in a 16 - lead, pb - free tssop .
ad5932 data sheet rev. a | page 4 of 28 specifications avdd = dvdd = 2.3 v to 5.5 v; agnd = dgnd = 0 v ; t a = t min to t max , unless otherwise noted. table 1 . y grade 1 parameter min typ max unit test conditions/comments signal dac specifications resolution 10 bits update rate 50 msps vout peak -to - peak 0.5 8 v internal 200 resistor to gnd vout offset 5 6 mv from 0 v to the trough of the waveform v midscale 0.3 2 v voltage at midscale output vout tc 200 ppm/c dc accuracy integral nonlinearity (inl) 1.5 lsb differential nonlinearity (dnl) 0.75 lsb dds specifications dynamic specifications signal -to - noise ratio 53 60 db f mclk = 50 mhz, f out = f mclk /4096 total harmonic distortion ?60 ?53 dbc f mclk = 50 mhz, f out = f mclk /4096 spurious - free dynamic range (sfdr) wide b and (0 to ny quist) ? 56 ?52 dbc f mclk = 50 mhz, f out = f mclk /50 narrow b and (200 khz) ?7 4 ?7 0 dbc f mclk = 50 mhz, f out = f mclk /50 clock feedthrough ?50 dbc up to 16 mhz out wake -u p time 1.7 ms from standby output buffer vout peak -to - peak 0 dvdd v typi cally, square wave on msbout and syncout output rise/fall time 2 12 ns voltage reference internal reference 1.15 1.18 1.26 v reference tc 2 90 pp m/c logic inputs 2 input current 0.1 2 a input high voltage , v inh 1.7 v dvdd = 2.3 v to 2.7 v 2.0 v dvdd = 2.7 v to 3.6 v 2.8 v dvdd = 4.5 v to 5.5 v input low voltage , v inl 0.6 v dvdd = 2.3 v to 2.7 v 0.7 v dvdd = 2.7 v to 3. 6 v 0.8 v dvdd = 4.5 v to 5.5 v input capacitance , c in 3 pf logic outputs 2 output high voltage , v oh dvdd ? 0.4 v v i sink = 1 ma output low voltage , v ol 0.4 v i sink = 1 ma floating - state o/p capacitance 5 pf power requirements f mclk = 50 mhz, f out = f mclk /7 avdd/dvdd 2.3 5.5 v i aa 3.8 4 ma i dd 2.4 2.7 ma i aa + i dd 6.2 6.7 ma
data sheet ad5932 rev. a | page 5 of 28 y grade 1 parameter min typ max unit test conditions/comments low power sleep mode device is reset before putting into stand by 20 85 a all outputs powered down, mclk = 0 v, serial interface active 140 240 a all outputs powered down, mclk active, serial interface active 1 operating temperature range is as follows: y version: ?40c to +125c; typical specifications are at +25c. 2 guaranteed by design, not production tested. specifications test circuit 10-bit dac sin rom a vdd regul a t or 20pf 10nf com p vout ad5932 cap/2.5v 12 100nf 10nf 05416-002 figure 2 . test circuit used to test the sp ecifications
ad5932 data sheet rev. a | page 6 of 28 timing specifications all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and are timed from a voltage level of (v il + v ih )/2 (s ee figure 3 to figure 6 ) . dvdd = 2.3 v to 5.5 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 limit at t min , t max unit conditions/comments t 1 20 ns min mclk period t 2 8 ns min mclk high d uration t 3 8 ns min mclk low duration t 4 25 ns min sclk period t 5 10 ns min sclk high time t 6 10 ns min sclk low time t 7 5 ns min fsync to sclk falling edge setup time t 8 10 ns min fsync to sclk hold time t 9 5 ns min data setup time t 10 3 ns min da ta hold time t 11 2 t 1 ns min minimum ctrl pulse width t 12 0 ns min ctrl rising edge to mclk falling edge setup time t 13 10 t 1 ns typ ctrl rising edge to vout delay (initial pulse, includes initialization) 8 t 1 ns typ ctrl rising edge to vout del ay (initial pulse, includes initialization) t 14 1 t 1 ns typ frequency change to sync output, each frequency increment t 15 2 t 1 ns typ frequency change to sync output, end of scan t 16 20 ns max mclk falling edge to msbout 1 guaranteed by design, not production tested. master clock and tim ing d iagrams mclk t 3 t 2 t 1 0 5416 -003 figure 3 . master clock sclk fsync sdat a d15 d14 d2 d1 d0 d15 d14 t 7 t 9 t 6 t 8 t 10 t 5 t 4 05416-004 figure 4 . serial timing
data sheet ad5932 rev. a | page 7 of 28 mclk ctr l v out t 12 t 1 1 t 13 05416-005 figure 5 . ctrl timing ctr l vout syncout (each frequency increment) syncout (end of scan) t 13 t 15 t 14 05416-006 figure 6 . syncout timing
ad5932 data sheet rev. a | page 8 of 28 absolute maximum rat ings t a = 25 c , unless otherwise noted. table 3 . parameter rating avdd to agnd ?0.3 v to +6.0 v dvdd to dgnd ?0.3 v to +6.0 v agnd to dgnd ?0.3 v to +0.3 v cap/2.5 v to dgnd ?0.3 v to + 2.75 v digital i/o voltage to dgnd ?0.3 v to dv dd + 0.3 v analog i/o voltage to agnd ?0.3 v to avdd + 0.3 v operating temperature range automotive (y version) ?40c to +125c storage temperature range ?65c to +150c maximum junction temperature +150c tssop (4 - layer board) ja thermal impedance 112c/ w jc thermal impedance 27.6c/w reflow soldering (pb - free) 300c peak temperature 260(+0/?5)c time at peak temperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
data sheet ad5932 rev. a | page 9 of 28 pin configuration an d func tion descriptions 05416-007 t op view (not to scale) 1 2 3 4 5 6 7 8 ad5932 16 15 14 13 12 1 1 10 9 a vdd dvdd cap/2.5v syncout mclk dgnd com p agnd st andb y fsync ctr l msbout interrupt sdat a sclk vout figure 7 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 comp dac bias pin. this pin is used for decoupling the dac bias voltage to avdd. 2 avdd po sitive power supply for the analog section. avdd can have a value from 2.3 v to 5.5 v. a 0.1 f decoupling capacitor should be connected between avdd and agnd. 3 dvdd positive power supply for the digital section. dvdd can have a value from 2.3 v to 5.5 v . a 0.1 f decoupling capacitor should be connected between dvdd and dgnd. 4 cap/2.5v digital circuitry. operates from a 2.5 v power supply. this 2.5 v is generated from dvdd using an on - board regulator. the regulator requires a decoupling capacitor of ty pically 100 nf, which is co nnected from cap/2.5 v to dgnd. if dvdd is equal to or less than 2.7 v, cap/2.5 v can be shorted to dvdd. 5 dgnd ground for all digital circuitry . 6 mclk digital clock input. dds output frequencies are expressed as a binary frac tion of the frequency of mclk. the output frequency accuracy and phase noise are determined by this clock. 7 syncout digital output for scan status inf ormation. user - selectable for end of scan (eos) or frequency increments through the control register (s yncop bit). this pin must be enabled by setting the synco ut en bit in the control register to 1. 8 msbout digital output. the inverted msb of the dac data is available at this pin. this output pin must be enabled by setting the msbouten bit in the control register to 1. 9 interrupt digital input. this pin acts as an interrupt during a frequency scan. a low -to - high transition is sampled by the internal mclk, which resets internal state machines. this results in the dac output going to midscale. 10 ctrl d igital input. triple function pin for initialization, start, and external frequency increments. a low - to - high transition, sampled by the internal mclk, is used to initialize and start internal state machines, which then execute the pre - programmed frequency s can sequence. when in auto - increment mode, a single pulse executes the entire scan sequence. when in external increment mode, each frequency increment is triggered by low -to - high transitions. 11 sdata serial data input. the 16 - bit serial data - word is a pplied to this input with the register address first , followed by the msb to lsbs of the data. 12 sclk serial clock input. data is clocked into the ad5932 on each falling sclk edge. 13 fsync active low control input. this is the frame synchronization signal for the serial data. when fsync is taken low, the internal logic is informed that a new word is being loaded into the device. 14 standby active high digital input. when this pin is high, the internal mclk is disabled, and the reference dac and re gulator are powered down. for optimum power sa ving, it is recommended that the ad5932 be reset before it is put into standby, as this results in a shutdown current of typically 20 a. 15 agnd ground for all analog circuitry. 16 v out voltage output. the analog outputs from the ad5932 are available here. an external resistive load is not required, because the device has a 200 resistor on board. a 20 pf capacitor to agnd is recommended to act as a low - pass filter and to reduce clock feedthrough.
ad5932 data sheet rev. a | page 10 of 28 typical performance characteristics mclk frequency (mhz) 9 8 7 6 4 3 5 2 1 0 0 50 45 40 35 30 25 20 15 10 5 05416-008 i dd (ma) t a = 25c a vdd = 5v msbou t , syncout enabled dvdd = 5v dvdd = 5 v , f out = mclk/7 dvdd = 3 v , f out = mclk/7 dvdd = 3v figure 8 . current consumption (i dd ) vs. mclk frequency f out (hz) 7 6 4 3 5 2 1 0 25mhz 20mhz 15mhz 10mhz 5mhz 2mhz 1mhz 500khz 100khz 10khz 1khz 500khz 05416-009 i dd (ma) t a = 25 c mclk = 50mhz msbout on, syncout on msbout of f , syncout off msbout on, syncout off msbout of f , syncout on figure 9. i dd vs. f out for various digital output conditions legend 1. sine w a ve outpu t , internal l y controlled swee p 2. triangular outpu t , internal l y controlled swee p 3. sine w a ve outpu t , external l y controlled swee p 4. triangular outpu t , external l y controlled swee p control option (see legend) 3.5 3.0 2.0 1.5 2.5 1.0 0.5 0 3 4 2 1 05416-010 i dd (ma) aidd didd figure 10 . i dd vs. output waveform type and control mclk frequency (mhz) ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 50 45 40 35 30 25 20 15 10 5 05416-011 sfdr (dbc) a vdd = dvdd = 3v/5v mclk = 50mhz c reg = 0 11 1 111 1 111 1 t a = 25c f out = mclk/7 f out = mclk/50 f out = mclk/3 figure 11 . wide - b and sfdr vs. mclk frequency mclk frequency (mhz) ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 50 45 40 35 30 25 20 15 10 5 05416-012 sfdr (dbc) a vdd = dvdd = 3v/5v mclk = 50mhz c reg = 0 11 1 111 1 111 1 t a = 25c f out = mclk/7 f out = mclk/50 f out = mclk/3 figure 12 . narrow - b and sfdr vs. mclk frequency f out (mhz) ?30 ?40 ?50 ?60 ?70 ?80 ?90 0.001 100 10 1 0.1 0.01 05416-013 sfdr (dbc) a vdd = dvdd = 3v/5v c reg = 0 11 1 111 1 111 1 t a = 25c mclk = 1mhz mclk = 10mhz mclk = 30mhz mclk = 50mhz figure 13 . wideband sfdr vs. f out for various mclk frequencies
data sheet ad5932 rev. a | page 11 of 28 mclk frequency (mhz) 70 65 60 55 50 45 40 50m 40m 30m 20m 10m 0 05416-014 snr (db) t a = 25c a vdd = dvdd = 5v f out = fmclk/4096 figure 14 . snr vs. mclk frequency temperature (c) 1.25 1.23 1.21 1.19 1.17 1.15 120 100 80 60 40 20 0 ?40 ?20 05416-015 v ref (v) a vdd = dvdd = 5v figure 15 . v ref vs. t emperature temperature (c) 2.0 1.8 1.9 1.7 1.6 1.5 1.3 1.4 1.2 120 100 80 60 40 20 0 ?40 ?20 05416-016 wake-up time (ms) a vdd = dvdd = 5v a vdd = dvdd = 2.3v figure 16 . wake - up time vs. temperature v p-p (mv) 05416-017 number of devices 0 10 20 30 40 50 60 70 80 90 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 figure 17 . histogram of vout peak - to - peak v offset (mv) 80 70 60 50 40 30 10 20 0 05416-018 number of devices 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 figure 18 . histogram of vout offset modulating frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?70 ?60 ?80 10 1m 100k 10k 1k 100 05416-019 attenuation (db) t a = 25c 100mv p-p ripple no decoupling on supplies a vdd = dvdd = 5v a vdd (on vout) dvdd (on cap/2.5v) figure 19 . pssr
ad5932 data sheet rev. a | page 12 of 28 frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100k 10k 1k 100 05416-020 phase noise figure 20 . output phase noise 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 100k 05416-021 (db) vwb 30 rwb 100 st 100 sec frequency (hz) figure 21 . f mclk = 10 mhz, f out = 2.4 khz, frequency word = 000fba 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 5m 05416-022 (db) vwb 300 rwb 1k st 50 sec frequency (hz) figure 22 . f mclk = 10 mhz, f out = 1.43 mhz = f mclk /7, frequenc y word = 249249 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 5m 05416-023 (db) vwb 300 rwb 1k st 50 sec frequency (hz) figure 23 . f mclk = 10 mhz, f out = 3.33 mhz = f mclk /3, frequency word = 555555 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 160k 05333-017 (db) vwb 30 rwb 100 st 200 sec frequency (hz) figure 24 . f mclk = 50 mhz, f out = 12 khz, frequency word = 000fba 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 1.6m 05416-025 (db) vwb 300 rwb 100 st 200 sec frequency (hz) figure 25 . f mclk = 50 mhz, f out = 120 khz, frequency word = 009d49
data sheet ad5932 rev. a | page 13 of 28 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05416-026 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 26 . f mclk = 50 mhz, f out = 1.2 mhz, frequency word = 0624dd 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05416-027 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 27 . f mclk = 50 mhz, f out = 4.8 mhz, frequency word = 189 374 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05416-028 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 28 . f mclk = 50 mhz, f out = 7.143 mhz = f mclk /7, frequency word = 249249 0 ?10 ?20 ?30 ?50 ?60 ?40 ?70 ?80 ?90 ?100 0 25m 05416-029 (db) vwb 300 rwb 1k st 200 sec frequency (hz) figure 29 . f mclk = 50 mhz, f out = 16.667 mhz = f mclk /3, frequency word = 555555
ad5932 data sheet rev. a | page 14 of 28 terminology integral nonlinearity ( inl) integral nonlinearity is t he maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale and full scale. the error is expressed in lsbs. differential nonlinearity (dnl) differential nonlinearity is t he difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. spurious - free dynamic range (sfd r) along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a dds device. the sfdr refers to the largest spur or harmonic that is present in the band of interest. the wide band sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to nyquist bandwidth. the narrow - band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz about the fundamental frequency. total harmonic distortion (thd) t otal harmonic distortion is t he ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad5932, thd is defined as: 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 ) db ( + + + + = w here : v 1 is the rms a mplitude of th e fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonic. signal -to - noise ratio (snr) the signal - to - noise ratio is t he ratio of the rms value of the measured output signal to the rms sum of all other spectral co mponents below the nyquist frequency. the value for snr is expressed in db . clock feedthrough there is feedthrough from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the ad5932 output spectrum.
data sheet ad5932 rev. a | page 15 of 28 theory of operation the ad5932 is a general - purpose , synthesized waveform generator capable of providing digitally programmable waveform sequences in both the frequency and time domain. the device contains embedded digita l processing to provide a scan of a user - programmable frequency profile allowing enhanced frequency control. because the device is pre programmable, it eliminates continuous write cycles from a dsp/microcontroller in ge nerating a particular waveform. freque ncy profile the frequency profile is defined by the start frequency (f start ), the frequency increment (f) and the number of increments per scan (n incr ). the increment interval between frequency increments, t int , is either user - programmable with the interv al automatically determined by the device (auto - increment mode), or externally controlled via a hardware pin (external increment mode). for automatic update, the interval profile can be for either a fixed number of clock periods or a fixed number of output waveform cycles. in the auto - increment mode, a single pulse at the ctrl pin starts and executes the frequency scan. in the external - increment mode, the ctrl pin also starts the scan, but the frequency increment interval is determined by the time interval between sequential 0/1 transitions on the ctrl pin . an example of a 2 - step frequency scan is shown in figure 30. note the frequency swept output si gnal is continuously available and is , therefore , phase continuo us at all frequency increments. 05416-030 2 1 number of step changes figure 30 . operation of the ad5932 when the ad5932 completes the frequency scan from frequency start to frequency end, that is, from f start incrementally to (f start + n incr f), it continues to output the last frequency in the scan (see figure 31) . note that the frequency scan time is given by (n incr + 1) t int . f st art midscale fina l frequenc y out 05416-031 figure 31 . frequency scan serial interface t he ad5932 has a standard 3 - wi re serial interface that is compatible with spi?, qspi?, microwire?, and dsp interface standards. data is loaded into the device as a 16 - bit word under the control of a serial clock input, sclk. the timing dia gram for this oper ation is shown in figure 4 . the fsync input is a level - triggered input that acts as a frame synchronizatio n and chip enable. data can be transferred into the device only when fsync is low. to start the serial data transfer, fsync should be taken low, observing the minimum fsync to sclk falling edge setup time, t 7 . after fsync goes low, serial data is shifted into the device's input shift register on the falling edges of sclk for 16 clock pulses. fsync may be taken high after the 16th falling edge of sclk, observing the minimum sclk falling edge to fsync rising edge time, t 8. alternatively, fsync can be kept low f or a multiple of 16 sclk pulses and then brought high at the end of the data transfer. in this way, a con tinuous stream of 16 - bit words can be loaded while fsync is held low. fsync should only go high after the 16th sclk falling edge of the last word is loaded. the sclk can be continuous, or, alternatively, the sclk can idle high or low between write operati ons. powering up the ad59 32 when the ad5932 is powered up, th e part is in an undefined state and , therefore, must be reset before use . the seven registers (control and frequency) contain invalid data and need to be set to a known value by the user. the con trol register should be the first register to be programmed, as this sets up the part. note that a write to the control register automatically resets the internal state machines and provides an analog output of midscale, because it p erform s the same functi on as the interrupt pin. typically, this is followed by a serial loading of all the required s can parameters. the dac output remains at midscale until a frequency scan is started using the ctrl pin.
ad5932 data sheet rev. a | page 16 of 28 programming the ad59 32 the ad5932 is designed to prov ide automatic frequency s cans when the ctrl pin is triggered. the scan is controlled by a set of registers, the addresses of which are given in table 5 . the function of each register is described in more detail in t he setting up the frequency scan section . the control register the ad5932 contains a 12 - bit control register that sets up the operating modes, as shown in the following bit map. d15 d14 d13 d12 d11 to d0 0 0 0 0 control bits this register controls the different functions and the various output options from the ad5932. table 6 describes the individual bits of the control register. to address the control register, d15 to d 12 of the 16 - bit serial word must be set to 0. table 5 . register addresses register address d15 d14 d13 d12 mnemonic name 0 0 0 0 c reg control bits 0 0 0 1 n incr number of increments 0 0 1 0 ? f lower 12 bits of delta frequency 0 0 1 1 ? f higher 12 bits of delta frequency 0 1 t int increment interval 1 0 reserved 1 1 0 0 f start lower 12 bits of start frequency 1 1 0 1 f start higher 12 bits of start frequency 1 1 1 0 reserved 1 1 1 1 reserved table 6 . description of bits in the control register bit name function d15 to d12 addr register a ddress bits. d11 b24 two write operations are required to load a complete word into the f start register and the f regi ster. when b24 = 1, a complete word is loaded into a frequency register in two consecutive writes. the first write contains the 12 lsbs of the frequency word and the next write contains the 12 msbs. refer to table 5 for the appropriate addresses. the write to the destination register occurs after both words have been loaded, so the register never holds an intermediate value. when b24 = 0, the 24 - bit f start /f register operates as two 12 - bit registers, one containing the 12 msbs and the other containing the 12 lsbs. this means that the 12 msbs of the frequency word can be altered independent ly of the 12 lsbs and vice versa. this is useful if the complete 2 4 - bit update is not required. to alter the 12 msbs or the 12 lsbs, a single write is made to the appropriate register address. refer to table 5 for the appropriate addresses. d10 dac enable when dac enable = 1, t he dac is enabled. when dac enable = 0, the dac is powered down. this saves power and is beneficial when using only the msb of the dac input data (available at the msbout pin). d9 sine/tri the function of this bit is to control what is available at the v out pin. when sine/tri = 1, the sin rom is used to convert the phase information into amplitude information, resulting in a sinusoidal signal at the output. when sine/tri = 0, the sin rom is bypassed, resulting in a triangular (up - down) output from the dac . d8 msbouten when msbouten = 1, the msbout pin is enabled. when msbouten = 0, the msbout is disabled ( three - state). d7 reserved this bit must be set to 1. d6 reserved this bit must be set to 1. d5 int/ext incr when int/ext incr = 1, the frequency increments are triggered externally through the ctrl pin. when int/ext incr = 0, the frequency increments are triggered automatically. d4 reserved this bit must be set to 1 . d3 syncsel this bit is active when d2 = 1. it is user - sel ectable to pulse at e nd of s can (eos) or at each frequency increment. when syncsel = 1, the synco ut pin outputs a high level at e nd of s can and returns to 0 at the start of the subsequent s can. when syncsel= 0, the synco ut outputs a pulse of 4 t clock only at each frequency increment. d2 syncouten when syncouten = 1, the sync output is available at the synco ut pin. when syncouten = 0, the s yncop pin is disabled (three - state ). d1 reserved this bit must be set to 1. d0 reserved this bit must be set to 1.
data sheet ad5932 rev. a | page 17 of 28 setting up the frequency scan as stated in the frequency profile section, the ad5932 requires certain registers to be programmed to enable a frequency scan. the setting up the frequency scan section discusses these registers in more detail. start frequency (f start ) to start a frequency scan, the user needs to tell the ad5932 what frequency to start scanning from. this frequency is stored in a 24-bit register called f start . if the user wishes to alter the entire contents of the f start register, two consecutive writes must be performed: one to the lsbs and the other to the msbs. note that for an entire write to this register, control bit b24 (d11) should be set to 1, with the lsbs programmed first. in some applications, the user does not need to alter all 24 bits of the f start register. by setting control bit b24 (d11) to 0, the 24-bit register operates as two 12-bit registers, one containing the 12 msbs and the other containing the 12 lsbs. this means that the 12 msbs of the f start word can be altered independently of the 12 lsbs and vice versa. the addresses of both the lsbs and the msbs of this register are shown in the following bit map. d15 d14 d13 d12 d11 to d0 1 1 0 0 12 lsbs of f start <110> 1 1 0 1 12 msbs of f start <2312> frequency increments ( f) the value in the f register sets the increment frequency for the scan and is added incrementally to the current output frequency. note that the increment frequency can be positive or negative, thereby giving an increasing or decreasing frequency scan. at the start of a scan, the frequency contained in the f start register is output. next, the frequency (f start + f ) is output. this is followed by (f start + f + f), and so on. multiplying the f value by the number of increments (n incr ) and adding it to the start frequency (f start ) give the final frequency in the scan. mathematically, this final frequency/stop frequency is represented by f start + ( n incr f) the f register is a 23-bit register that requires two 16-bit writes to be programmed. table 7 gives the addresses associated with both the msb and lsb registers of the f word. table 7. f register bits d15 d14 d13 d12 d11 d10 to d0 scan direction 0 0 1 0 12 lsbs of f <110> n/a 0 0 1 1 0 11 msbs of f <2212> positive f (f start + f) 0 0 1 1 1 11 msbs of f <2212> negative ? f (f start ? f) number of increments (n incr ) an end frequency is not required on the ad5932. instead, this end frequency is calculated by multiplying the frequency increment value (f) by the number of frequency steps (n incr ) and adding it to/subtracting it from the start frequency (f start ); that is, f start + n incr f. the n incr register is a 12-bit register, with the address shown in the following bit map. d15 d14 d13 d12 d11 d0 0 0 0 1 12 bits of n incr <110> the number of increments is programmed in binary fashion, with 000000000010 representing the minimum number of frequency increments (two increments) and 111111111111 representing the maximum number of increments (4095). table 8. n incr data bits d11 d0 number of increments 0000 0000 0010 two frequency increments. this is the minimum number of frequency increments. 0000 0000 0011 three frequency increments. 0000 0000 0100 four frequency increments. 1111 1111 1110 4094 frequency increments. 1111 1111 1111 4095 frequency increments. increment interval (t int ) the increment interval dictates the duration of the dac output signal for each individual frequency of the frequency scan. the ad5932 offers the user two choices: ? the duration is a multiple of cycles of the output frequency. ? the duration is a multiple of mclk periods. the desired choice is selected by bit d13 in the t int register as shown in the following bit map. d15 d14 d13 d12 d11 d10 to d0 0 1 0 x x 11 bits <100> fixed number of output waveform cycles. 0 1 1 x x 11 bits <100> fixed number of clock periods. programming of this register is in binary form, with the minimum number being decimal 2. note that 11 bits, d10 to d0, of the register are available to program the time interval. as an example, if mclk = 50 mhz, then each clock period/base interval is (1/50 mhz) = 20 ns. if each frequency must be output for 100 ns, then <00000000101> or decimal 5 must be pro- grammed to this register. note that the ad5930 can output each frequency for a maximum duration of 211 ? 1 (or 2047) times the increment interval.
ad5932 data sheet rev. a | page 18 of 28 therefore, in this example, a time interval of 20 ns 2047 = 40 s is the maximum, with the minimum being 40 ns. for some applications, this maximum time of 40 s may be i nsufficient. therefore, to allow for sweeps that need a longer increment interval, time - base multipliers are provided. d12 and d11 are dedicated to the time - base multipliers , as shown in the bit map above . a more detailed table of the multiplier options is given in table 9 . table 9 . time - base multiplier values d12 d11 m ultiplier value 0 0 multiply (1/mclk) by 1 0 1 multiply (1/mclk) by 5 1 0 multiply (1/mclk) by 100 1 1 multiply (1/mclk) by 500 if mclk = 50 mhz and a multiplier of 500 is used, then the base interval (t base ) is now (1/(50 mhz) x 500)) = 10 s. using a multiplier of 500, the maximum increment interval is 10 s 2 11 ? 1 = 20.5 ms. therefore, the option of time - base multipliers gives the user enhanced flexibility when programming the length of the frequency window, because any frequency can be output for a minimum of 40 ns up to a maximum of 20.5 ms. the a bove example shows a fixed number of clock perio ds. n ote that the same equally applies to fixed numbers of clock cycles. length of scan time the length of time to complete a user - programmed frequency s can is given by the following equation: t scan = (1 + n incr ) t base activating and contr olling the scan after the registers have been programmed, a 0 to 1 transit ion on the ctrl pin starts the scan. the s can always starts from the frequency programmed into the f start register. it changes by the value in the ? f register and increases by the number of steps in the n incr register. however, the time interval of each frequency can be internally controlled using the t int register or externally controlled using the ctrl pin. the available options are ? auto - increment ? e xternal inc rement auto - increment control the value in the t int r egister is used to control the s can. the ad5932 outputs each frequency for the length of time pro - grammed in the t int register, before moving on to the next frequency. to s e t up the ad59 32 to this mode, int/ext incr ( bit d5) must be set to 0. external increment control in this case, the time interval, t int , is set by the pulse rate on the ctrl pin. the first 0 to 1 tr ansition on the pin starts the s can. each subsequent 0 to 1 transition on the ctrl pin increments the output frequency by the value programmed into the ? f register. to s e t up the ad5932 to this mode, int/ext incr ( bit d5) must be set to 1. i nterrupt pin this function is used as an interrupt during a frequency s can. a low - t o - high transition on this pin is sampled by the internal mclk, thereby resetting internal state machines, which results in the output going to midscale. s tandby pin sections of the ad5932 that are not in use can be powered down to minimize power consumpti on. this is done b y using the standby pin. for optimum power savings, it is recom - mended to reset the ad5932 before entering standby. d oing so reduces the power - down current to 20 a. when this pin is high, the internal mclk is disabled, and the reference, dac, and regulator are powered down. when in this state, the dac output of the ad5932 remains at its present value, because the nco is no longer accumulating. when the device is taken back out of standby mode, the mclk is re - activated , and the s can continues. to ensure correct operation for new data, it is recommended that the device be internally reset , using a control register write or using the interrupt pin, and then restarted .
data sheet ad5932 rev. a | page 19 of 28 outputs from the ad5 932 the ad5932 offers a variety of outputs from the chip. the analog outputs are available f rom the vout pin and include a sine wave and a triangle output. the digital out puts are available from the msb out pin and the syncout pin. analog outputs sinusoidal output the sin rom is used to convert the phase information from the frequency register i nto amplitude information, resulting in a sinusoidal signal at the output. the ad5932 includes a 10- bit, high imped ance , current source dac that is configured for single - ended operation. an external loa d resistor is not required because the device has a 200 r esistor on board. to have a sinusoidal output fr om the vout pin, set sine/tri ( bit d9) in the control register to 1. triangle output the sin rom can be bypassed so that the truncated digital output from the nco is sent to the dac. in this case, the outp ut is no longer sinusoidal. the dac produces a 10 - bit linear triangular function. to have a triangle output fro m the vout pin, set sine/tri ( bit d9) to 0. note that dac e nable ( bit d10) must be set to 1 (that is, the dac is enabled) when using this pin. vout max 3p/2 7p/2 p/2 5p/2 9p/2 1 1p/2 vout min 05416-032 figure 32 . triangle output digital outputs square - wave output from msb out the inverse of the msb from the nco can be output from the ad5932 . by setting msbouten ( bit d8) to 1, the inverted msb of the dac d ata is available at the m sb out pin. this is useful as a digital clock source. dvdd dgnd 05416-040 figure 33 . msb output syncout p in the syncout pin can be used t o give the status of the scan. it is us er - selectable for the end of scan or to output a 4 t clock pulse at fre quency increments. the timing information for both of these modes is shown in figure 6 . the syncout pin must be enabled before use. this is done using bit d2 in the control register. the output available from this pin is then controlled by bit d3 in the control register. see table 6 for more information.
ad5932 data sheet rev. a | page 20 of 28 applications grounding and layout the printed circuit board that houses the ad5932 should be designed so that the analo g and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it gives the best shielding. digit al and analog ground planes should be joined in only one place. if the ad5932 is th e only device requiring an agnd - to - dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad5932. if the ad5932 is in a system wher e mu ltiple devices require agnd - to - dgnd connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the ad5932. avoid running d igital lines under the device because these couple noise ont o the die. the analog ground plane should run under the ad5932 to avoid noise coupling. the power supply lines to the ad5932 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to eac h other, reducing the effects of feedthrough . a microstrip technique is by far the best but is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the other side. good decoupling is important. the analog and digital supplies to the ad5932 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd, respectively, with 0.1 f ceramic capacitors in parallel with 10 f tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in s ystems where a common supply is used to drive both the avdd and dvdd of the ad5932, it is recommended that the systems avdd supply be used. this supply should have the recom - mended analog supply decoupling between the avdd pin of the ad5932 and agnd and t he recommended digital supply decoupling capacitors between the dvdd pin and dgnd. interfacing to microprocessors the ad5932 has a standard serial interface that allows the part to interface directly with several microprocessors. the device uses an exte rnal serial clock to write the data/control informa - tion into the device. the serial clock can have a frequency of 40 mhz maximum. the serial clock can be continuous, or it can idle high or low between write operations. when data/control information is b eing written to the ad5932, fsync is taken low and is held low while the 16 bits of data are being written into the ad5932. the fsync signal frames the 16 bits of information being loaded into the ad5932. ad5932 to adsp - 21xx interface figure 34 shows the serial interface between the ad5932 and the adsp - 21xx . the adsp - 21xx should be set up to operate in the sport transmit alternate fr aming mode (tfsw = 1). the adsp - 21xx are programmed through the sport control register and should be configured as follows: ? internal clock operation (isclk = 1) ? active low framing (invtfs = 1) ? 16- bit word length (slen = 15) ? internal frame sync signal (itf s = 1) ? generation of a frame sync for each write (tfsr = 1) transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the serial clock and clocked into the ad5932 on the sclk falling edge. ad5932 1 adsp-2101/ adsp-2103 1 1 additiona l pins omitted for clarit y . tfs dt sclk fsync 05416-034 sdat a sclk figure 34 . adsp - 2101/adsp - 2103 to ad5932 interface
data sheet ad5932 rev. a | page 21 of 28 ad5932 to 68hc11/68l 11 interface figure 35 shows the serial interface between the ad5932 and the 68hc11/68l11 microc ontroller. the microcontroller is configured as the master by s etting b it mstr in the spcr to 1, which provides a serial clock on sck while the mosi output drives the serial d ata line , sdata. because the micro controller does not have a dedicated frame sync pin, the fsync signal is derived from a port line (pc7). the set - up conditions for correct operation of the interface are as follows: ? sck idles high between write operations (cpol = 0) . ? data is valid on the sck falling edge (cpha = 1) . when data is being transmitted to the ad5932, the fsync line is taken low (pc7). serial data from the 68hc11/68l11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is trans mitted msb first. in order to load data into the ad5932, p c7 is held low after the first eight bits are transferred and a second serial write operation is performed to the ad5932. only after the second eight bits have been transferred should fsync be taken high again. ad5932 1 68hc 1 1/68l 1 1 1 1 additiona l pins omitted for clarit y . pc7 mosi sck fsync 05416-035 sdat a sclk figure 35 . 68hc11/68l11 to ad5932 interface ad5932 to 80c51/80l5 1 interface figure 36 shows the serial interface between the ad5932 and the 80c51/80l51 microcontroller. the micro controller is operated in m ode 0 so that tx d of the 80c51/80l51 drives sclk of the ad5932 , while rx d drives the serial data line sdata. the fsync signal is again derived from a bit program - mable pin on the port (p3.3 being used in the diagram). when d ata is to be transmitted to the ad5932, p3.3 is taken low. the 80c51/80l5 1 transmits data in 8 - bit bytes; thus, only eight falling sclk edges occur in each cycle. to load the remaining eight bits to the ad5932, p3 .3 is held low after the first eight bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. p3.3 is taken high following completion of the second write operation. sclk should idle high between the two write operations. the 80c51/80l51 outputs th e serial data in a n lsb - first format. the ad5932 accepts the msb first (the four msbs being the control information, the next four bi ts being the address, while the eight lsbs contain the data when writing to a destination register). therefore, the transmi t routine of the 80c51/8 0l51 must consider this and rearrange the bits so that the msb is output first. ad5932 1 80c51/80l51 1 1 additiona l pins omitted for clarit y . p3.3 rxd txd fsync 05416-036 sdat a sclk figure 36 . 80c51/80l51 to ad5932 interface ad5932 to dsp56002 i nterface figure 37 s hows the interface between the ad5932 and the dsp56002. the dsp56002 is configured for normal mode, asynchronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated internally (sc2 = 1), the transfers are 16 bits wide (wl1 = 1, wl0 = 0), and the frame sync signal frames the 16 bits (fsl = 0). the frame sync signal is available on pin sc2, but it must be inverted before being applied to the ad5932. the interface to the dsp56000/dsp56001 is similar to that of th e dsp56002. ad5932 1 dsp56002 1 1 additiona l pins omitted for clarit y . sc2 std sck fsync 05416-032 sdat a sclk figure 37 . dsp56002 to ad5932 interface
ad5932 data sheet rev. a | page 22 of 28 evaluation board the ad5932 evaluation board allows designers to evaluate the high performance ad5932 dds modulator with minimum effort. the evaluation board interfa ces to the usb port of a pc. it is possib le to power the entire board from the usb port. all that is needed to complete the evaluation of the chip is either a spectrum analyzer or a scope. the dds evaluation kit includes a populated and tested ad5932 pri nted circuit board. the eval - ad5932eb kit is shipped with a cd - rom that includes self - installing software. the pc is connected to the evaluation board using the supplied cable. the software is compatible with microsoft? windows? 2000 and windows xp . a sch ematic of the evaluation board is shown in figure 38 and figure 39. using the ad5932 evaluation board the ad5932 evaluation kit is a test system designed to simplify the ev aluation of the ad5932. an application note is also availab le with the evaluation board that gives full information on operating the evaluation board. prototyping area an area is available on the evaluation board for the user to add additional circuits to the evaluation test set. users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. xo vs. external clock the ad5932 can operate with master clocks up to 50 mhz. a 50 mhz o scillator is included on the evaluation board. however, this oscillator can be removed and, if required, an external cmos clock can be connected to the part.
data sheet ad5932 rev. a | page 23 of 28 schematic s 05416-038 figure 38 . page 1 of eval - ad5932eb schematic
ad5932 data sheet rev. a | page 24 of 28 05416-039 figure 39 . page 2 of eval - ad5932eb schematic
data sheet ad5932 rev. a | page 25 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 40 . 16 - lead thin shrink small outline package (tssop) (ru - 16) dimensions shown in millimeters ordering guide model 1 temperature range pack age description package option ad5932yruz ? 40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 ad5932yruz - reel7 ? 40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 eval - ad5932eb z evaluation board 1 z = rohs compliant part.
ad5932 data sheet rev. a | page 26 of 28 notes
data sheet ad5932 rev. a | page 27 of 28 notes
ad5932 data sheet rev. a | page 28 of 28 notes ? 2006 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05416 - 0- 2/12(a)

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